1. Field of the Invention
This invention relates to an erasable and programmable nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having offset transistors and a method for manufacturing the same.
2. Description of the Related Art
Conventionally, a transistor used as an EPROM memory cell is constructed as shown in FIG. 1, for example. That is, n-type source and drain regions 102 which are separated by a preset distance from each other are formed in the main surface area of a p-type semiconductor substrate 101. A laminated structure of a first insulation film 103, a floating gate 104 of a first polysilicon layer, a second insulation film 105 and a control gate 106 formed of a second polysilicon layer is disposed on that portion of the substrate 101 which lies between the source and drain regions 102.
In a transistor (memory cell) with the above laminated gate structure, the threshold voltage thereof varies according to whether or not electrons are stored in the floating gate 104. For convenience, the transistor constituted to include the floating gate and the control gate is hereinafter referred to as a floating gate transistor. Memory data is read out from the memory cell according to a difference in the threshold voltages. For example, when a word line is selected by a row decoder, a voltage of 5 V is applied to the control gate of the floating gate transistor connected to the selected word line. At this time, whether the floating gate transistor is turned on or off is determined according to whether the threshold voltage is high or low, that is, whether electrons are injected into the floating gate or not. More specifically, the drain of the floating gate transistor is connected to a bit line which is in turn connected to a power source via a load element. When the threshold voltage is low (when no electron is stored in the floating gate), the floating gate transistor is turned on, causing a current to flow from the power source to the ground via the load element, the bit line and the floating gate transistor. As a result, the bit line is discharged and is set to a low potential level. Assume that data "1" is stored in this case. Then, the memory data "1" is determined by sensing the low potential by means of a sense amplifier. On the other hand, when the threshold voltage is high (when electrons are injected into the floating gate), the floating gate transistor is kept in the off condition, the bit line is charged by means of the power source via the load element and is set to a high potential level. The high potential is sensed by the sense amplifier and storage of data "0" is determined.
A method of injecting electrons into the floating gate 104 is effected by applying a high voltage between the control gate 106 and the drain 102 of the floating gate transistor to generate hot electrons and inject the hot electrons into the floating gate 104.
A method of emitting electrons is effected by applying 0 v to the control gate of the floating gate transistor and applying a high voltage to the drain 102 so as to emit the electrons from the floating gate 104 to the drain 102 by use of the tunnel effect of the first insulation film 103.
Injection of electrons into the floating gate 104 and emission of electrons from the floating gate 104 are effected by using the above two methods and thus data can be electrically programmed and erased in the memory cell of FIG. 1.
FIG. 2 shows a memory cell array constituted by use of memory cells of the structure shown in FIG. 1 and a peripheral circuit thereof. Memory cells MC11, MC12, MC13, ---, MC21, MC22, MC23, ---, MC31, MC32, MC33, --- are arranged in a matrix form. The control gates of the memory cells MC on the same row are connected to a corresponding one of word lines WL1, WL2, WL3, ---, the drains of the memory cells MC on the same column are connected to a corresponding one of bit lines BL1, BL2, BL3, --- and each of the sources of the memory cells MC is grounded. Outputs of a row decoder RD are supplied to the word lines WL1, WL2, WL3, --- and outputs of a column decoder CD are supplied to the bit lines BL1, BL2, BL3, ---.
In a case where the memory data of the memory cell MC is electrically erased, a plurality of floating gate transistors MC which are arranged on the same column (which are connected to the same bit line BL) are used as one unit. That is, the memory data of the floating gate transistors MC which are arranged on the same column are electrically erased at the same time. For example, the memory data of the memory cells MC21, MC22, MC23, --- are erased at the same time by setting all the word lines WL1, WL2, WL3, -- to 0 V and applying a high voltage to the bit line BL2.
In the conventional EPROM as described above, the operation of extracting electrons is effected with respect to the memory cells MC on the same column. Therefore, if the amounts of electrons stored in the floating gates 104 of the memory cells MC connected to the same bit line are different, it becomes necessary to continuously apply a high voltage to the bit line until all the electrons are extracted from the floating gate which has the largest amount of electrons stored therein. For this reason, electrons may be excessively extracted from the floating gate 104 of the memory cell MC which has little electrons stored therein and the floating gate will be positively charged. This is called excessive erasing condition. Assume, for example, that data "1" is stored in the memory cell MC2 and data "0" is stored in the other memory cells MC22, MC23, ---. That is, a sufficiently large amount of electrons are stored in the floating gate 104 of the memory cells MC22, MC23, --- and few electrons are stored in the floating gate 104 of the memory cell MC21. If, in this condition, a high voltage is applied to the bit line BL2 to simultaneously erase the memory data of the memory cells MC21, MC22, MC23, ---, then the memory cell MC21 is set into the excessive erasing condition. when the memory cell MC is set into the excessive erasing condition, then the memory cell is converted into a depletion type and the threshold voltage thereof becomes negative. As a result, a current will flow between the source and drain even when the potential of the control gate 106 or the potential of the word line WL1 is 0 V (ground potential).
Assume now that the memory cell MC21 is set in the excessive erasing condition and the memory cell MC22 is set in the data "0" programmed condition (in which electrons are stored in the floating gate thereof) in the EPROM of FIG. 2. Then, the bit line BL2 is selected by the column decoder CD and supplied with a voltage of 2 V and the other bit lines BL1, BL3, --- are set into an open condition in order to select the memory cell MC22. Further, the word line WL2 is selectively supplied with a voltage of 5 V by means of the row decoder RD and the other word lines WL1, WL3, --- are set to the ground potential, for example, 0 V. Since the memory cell MC22 thus selected has data "0" stored therein, the floating gate transistor is kept turned off and no cell current will flow therein. Therefore, theoretically, the potential of the bit line BL2 does not vary and data "0" may be read out as the result of sensing operation of a sensing amplifier (not shown). However, in a case where the memory cell MC21 which is set in the excessive erasing condition is present on the same bit line BL2, the floating gate transistor of the memory cell MC21 is converted into the depletion type. Therefore, even if the control gate thereof is set at 0 V, a cell current flows, changing the potential of the bit line BL2. The potential change is read by means of the sense amplifier and it is erroneously determined that data "1" is stored in the selected memory cell MC22. That is, an erroneous operation occurs. In order to prevent occurrence of the excessive erasing condition due to the difference in the initially stored data (the presence of memory cells storing data "1" and data "0" on the same column), the programming operation is effected with respect to all the memory cells MC before the erasing operation so as to set all the memory cells MC into the condition in which a sufficiently large amount of electrons are stored (initialization) and then the erasing operation is effected.
Further, if the erasing period of time is too long, an excessive amount of electrons may be extracted from the floating gate and the excessive erasing condition occurs. In order to prevent this occurrence, the erasing verifying method is used in the prior art. In the erasing verifying method, when the memory data is electrically erased, a high voltage in the form of short pulse wave is applied to the drain and data is read out each time the pulse is applied. That is, electrons are extracted slowly by little and the erasing condition is checked after each pulse applying operation so as to prevent occurrence of the excessive erasing condition. However, the erasing operation is extremely complicated and the time for completing the erasing operation becomes long, considerably degrading the function of the semiconductor memory device.
In order to solve the above problems, another method is proposed in which a transistor having no floating gate is arranged adjacent to the floating gate transistor in a lengthwise direction of a channel. For convenience, the transistor having no floating gate is referred to as an offset transistor. The gate of the offset transistor is connected to the same word line to which the control gate of the floating gate transistor is connected.
Now, the memory cell having the offset transistor is explained with reference to FIGS. 3 and 4.
FIG. 3 is a cross sectional view of a memory cell having the offset transistor in which n-type source and drain regions 102 separated by a preset distance from each other are formed in the main surface area of a p-type semiconductor substrate 101. A first insulation film 103 is formed on that portion of the substrate 10 which lies between the source and drain regions 102 and a floating gate 104 formed of a first polysilicon layer is formed on the insulation film 103. A second insulation film 105 is formed on the floating gate 104 and that portion of the substrate 102 which lies between the source and drain regions 102 and on which the insulation film 103 is not formed and a control gate 106 formed of a second polysilicon layer is formed on the insulation film 105. Portion 106A of the control gate 106 acts as a control gate of the floating gate transistor and portion 106B of the control gate 106 acts as a gate of the offset transistor.
With the memory cell of the above construction, since the offset transistor arranged adjacent to the floating gate transistor has no floating gate 104, the offset transistor will not be turned on if the control gate 106 is kept at the ground potential even in a case where the floating gate 104 is set into the excessive erasing condition and the floating gate transistor is converted into the depletion type. As a result, no cell current will flow even if the floating gate 104 is set into the excessive erasing condition and the floating gate transistor is converted into the depletion type.
FIG. 4 shows a memory cell array formed by using the memory cell shown in FIG. 3 and a peripheral circuit thereof. Assume that a memory cell MC21 is set into the excessive erasing condition and a memory cell MC22 is set into the data "0" programmed condition. In order to select the memory cell MC22, a bit line BL2 is selected by a column decoder CD and supplied with a voltage of 2 V and the other bit lines BL1, BL3, --- are set into the open condition. At the same time, a word line WL2 is selected by means of a row decoder RD and supplied with a voltage of 5 V and the other word lines WL1, WL3, --- are set at the ground potential, for example, 0 V. Since the memory cell MC22 thus selected has data "0" stored therein, the floating gate transistor is turned off. Therefore, no cell current flows therein and the potential of the bit line BL2 does not change so that data "0" may be read out as the result of the sensing operation of a sense amplifier (not shown). At this time, the memory cell MC21 which is set into the excessive erasing condition is connected to the bit line BL2 However, the memory cell MC21 has the offset transistor and is kept in the turn-off condition if the control gate thereof is set at the ground potential (0 V). Therefore, the memory cell MC21 set in the excessive erasing condition will not affect the potential of the bit line BL2. As a result, even if a memory cell set in the excessive erasing condition is present on the same bit line to which the selected memory cell MC22 is connected, the memory data can be correctly read out from the memory cell MC22.
However, in the memory cell having the offset transistor, it is necessary to provide an offset transistor forming area in the element formation area since an offset transistor section is formed in each memory cell, thus preventing the miniaturization of the elements.
As described above, the nonvolatile semiconductor memory device having offset transistors, various problems caused by the presence of a memory cell set in the excessive erasing condition can be solved but the miniaturization thereof becomes difficult because of its structure and the integration density cannot be easily enhanced.